1. Field of the Invention
The invention concerns a circuit arrangement for a reception part of an SDH (Synchronous Digital Hierarchy) Transmission System and a circuit arrangement for a transmission part of an SDH transmission system.
2. Description of the Prior Art
SDH is a special transmission hierarchy for the transmission of digital signals. By means of the synchronous digital hierarchy it is possible to transmit plesiochronous signals uniformly. At that several binary signals are called plesiochronous if their bit rates are nominally equal, but in fact are able to deviate within a given tolerance from the nominal value. It is possible to transmit several plesiochronous signals via the time-multiplex process by means of one transmission channel (SDH transmission channel). Before the plesiochronous signals are combined by a multiplexer (SDH multiplexer) and before they can be transmitted on the SDH transmission channel, they must be brought in the reception part to the same bit rate. The adaptation of the bit rates occurs in the reception part, especially through bit- or pointer-stuffing actions. In the transmission portion the plesiochronous signals are regained from the synchronous signal stream and placed together with their associated plesiochronous signal clocks on the output channels assigned to them.
For the synchronization of the parallel plesiochronous signal streams it is conceivable to realize the reception part through parallel circuits, in which parallel processing of the plesiochronous signals occurs. In an analogous manner it is also possible that the signals transmitted in the SDH transmission channel be processed in parallel circuits into parallel plesiochronous signals. A disadvantage is here the fact that the expenses for the circuit technology increase strongly with the rising number of input channels assigned to the reception part or output channels assigned to the transmission part.